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8XC196KB ADVANCED 16-BIT CHMOS MICROCONTROLLER ROMless OR ROM
Automotive
Y Y Y Y Y Y Y Y Y Y Y
b 40 C to a 125 C Ambient
Y
232 Bytes of On-Chip Register RAM 8 Kbytes of On-Chip ROM (Optional) High-Performance CHMOS Process Register-to-Register Architecture 10-Bit A D Converter with S H Five 8-Bit I O Ports 28 Interrupt Sources Pulse Width Modulated Output Powerdown and Idle Modes High Speed I O Subsystem
Y Y Y Y Y Y Y Y Y
Dynamically Configurable 8 16-Bit Buswidth Full Duplex Serial Port Dedicated Baud Rate Generator 1 725 ms 16 x 16 Multiply 3 ms 32 16 Divide 16-Bit Watchdog Timer 16-Bit Timer 16-Bit Up Down Counter w Capture Four 16-Bit Software Timers HOLD HOLDA Bus Protocol
The 8XC196KB 16-bit microcontroller comes with 8 Kbytes of on-chip mask programmable ROM or in ROMless versions All devices are high performance members of the 8096 microcontroller family The 8XC196KB is pin-to-pin compatible and uses a true superset of the 8096 instructions Intel's CHMOS process provides a high performance processor along with low power consumption To further reduce power requirements the processor can be placed into Idle or Powerdown Mode Bit byte word and some 32-bit operations are available on the 8XC196KB With a 16 MHz oscillator a 16-bit addition takes 0 495 ms and the instruction times average 0 375 ms to 1 125 ms in typical applications Four high-speed capture inputs are provided to record times when events occur 4 a 2 high-speed outputs are available for pulse or waveform generation The high-speed output can also generate four software timers or start an A D conversion Events can be based on the 16-bit timer or a 16-bit up down counter Also provided on-chip are an 8 channel 10-bit A D converter with Sample and Hold a serial port with synchronous asynchronous modes and on-chip baud rate generator a 16-bit watchdog timer pulse width modulated output with prescaler and an on-chip clock failure detect circuitry
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Figure 1 8XC196KB Block Diagram
Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata
COPYRIGHT
INTEL CORPORATION 1995
February 1995
Order Number 270679-005
AUTOMOTIVE 8XC196KB
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Figure 2 The 8XC196KB Family Nomenclature
ARCHITECTURE
The 8XC196KB is a member of the 8096 family as such has the same architecture and uses the same instruction set as the 8096 Many new features have been added on the 8CX196KB including CPU FEATURES Divide by 2 instead of divide by 3 clock for a 1 5 c performance improvement Faster instructions especially indexed indirect data operations 1 725 ms 16 x 16 multiply with 16 MHz clock (is 6 25 ms on the 8096) Faster interrupt response (almost twice as fast) Powerdown and Idle Modes 6 new instructions 8 new interrupt vectors 6 new interrupt sources PERIPHERAL FEATURES SFR window switching allows read-only SFRs to be written and vice-versa Timer 2 can count up and down by external selection
Timer 2 has an independent capture register on rising edges of (P2 7) HSO line events are stored in a register HSO has CAM lock and CAM clear commands New baud rate values are needed for serial port which enables higher speeds in all modes Double buffered serial port transmit register (before only receive was double buffered) Serial port receive overrun and framing error detection PWM has a divide by 2 prescaler HOLD HLDA bus protocol THERMAL CHARACTERISTICS PLCC iJA iJC Max Case Temperature 35 C W 12 C W 135 C
NEW INSTRUCTIONS PUSHA PUSHes the PSW IMASK IMASK1 and WSR (used instead of PUSHF when using the new interrupts and registers) POPA POPs the PSW IMASK IMASK1 and WSR (used instead of POPF when using the new interrupts and registers)
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AUTOMOTIVE 8XC196KB
IDLPD Sets the device into Idle or Powerdown Mode The instruction has the following format IDLPD key (where key e 1 for Idle and key e 2 for Powerdown Illegal keys are processed but no action is taken Compare 2 long direct values Only the direct addressing mode is supported for this instruction and the format follows the CMP format Block move using 2 auto-incrementing pointers and a counter The instruction has the following format BMOV IPTR wCNT The IPTR is a long word with the low word being the address of the source and the upper word being the address of the destination wCNT is the number of words to be transferred DJNZW Decrement Jump Not Zero using a word counter The instruction format follows the DJNZ instruction
See the Functional Deviations section for details
CMPL
SFR OPERATION All of the registers that were present on the 8096 work the same way as they did except that the baud rate value will be different on the 8XC196KB The new registers shown in the memory map control new functions The most important register is the Window Select Register (WSR) which allows the reading of the formerly write-only registers and vice-versa PACKAGING The 8XC196KB is available in 68-pin plastic leaded chip carrier (PLCC) and 68-pin CERQUAD packages Contact your local sales office to determine the exact ordering code for the part desired
BMOV
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Figure 3 68-Pin PLCC Package
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AUTOMOTIVE 8XC196KB
PLCC 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44
Description ACH7 PO 7 PMD3 ACH6 PO 6 PMD2 ACH2 PO 2 ACH0 PO 0 ACH1 PO 1 ACH3 PO 3 NMI EA VCC VSS XTAL1 XTAL2 CLKOUT BUSWIDTH INST ALE ADV RD AD0 P3 0 AD1 P3 1 AD2 P3 2 AD3 P3 3 AD4 P3 4 AD5 P3 5 AD6 P3 6 AD7 P3 7 AD8 P4 0 AD9 P4 1 AD10 P4 2 AD11 P4 3 AD12 P4 4 AD13 P4 5 AD14 P4 6 AD15 P4 7 T2CLK P2 3
PLCC 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
Description READY T2RST P2 4 AINC BHE WRH WR WRL PWM P2 5 P2 7 T2CAPTURE PACT VPP VSS HSO 3 HSO 2 P2 6 P1 7 HOLD P1 6 HLDA P1 5 BREQ HSO 1 HSO 0 HSO 5 HSI 3 SID3 HSO 4 HSI 2 SID2 HSI 1 SID1 HSI 0 SID0 P1 4 P1 3 P1 2 P1 1 P1 0 TXD P2 0 PVER RXD P2 1 PALE RESET EXTINT P2 2 PROG VSS VREF ANGND ACH4 P0 4 PMD0 ACH4 P0 5 PMD1
Figure 4 PLCC Functional Pinouts
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AUTOMOTIVE 8XC196KB
PIN DESCRIPTIONS
Symbol VCC VSS VREF Main Supply Voltage ( a 5V) Digital Circuit Ground (0V) There are three VSS pins all of which MUST be connected Reference for the A D Converter ( a 5V) VREF is also the supply voltage to the analog portion of the A D converter and the logic used to read Port 0 Must be connected for A D and Port 0 to function Reference Ground for the A D Converter Must be held at nominally the same potential as VSS Programming Voltage for the EPROM Parts It should be a 12 75V for programming This pin was VBB on 8X9X-90 parts It is also the timing pin for the return from powerdown circuit Connect this pin with a 1 mF capacitor to VSS and a 1 MX resistor to VCC If this function is not used VPP may be tied to VCC Input of the Oscillator Inverter and the Internal Clock Generator Output of the Oscillator Inverter Output of the Internal Clock Generator The frequency of CLKOUT is frequency It has a 50% duty cycle the oscillator Name and Function
ANGND VPP
XTAL1 XTAL2 CLKOUT RESET
Reset Input to the Chip Input low for at least 4 state times will reset the chip The subsequent low to high transition resynchronizes CLKOUT and commences a 10-state time sequence in which the PSW is cleared a byte is read from 2018H loading the CCB and a jump to location 2080H is executed Input high for normal operation RESET has an internal pullup Input for Bus Width Selection If CCR bit 1 is a one this pin selects the buswidth for the bus cycle in progress If BUSWIDTH is low an 8-bit cycle occurs If BUSWIDTH is high a 16-bit cycle occurs If CCR bit 1 is a 0 the bus is always an 8-bit bus This pin is the TEST pin on the 8X9X-90 parts Systems with TEST tied to VCC need NOT change A positive transition causes an interrupt vector through external memory location 203EH Output High during an External Memory Read Indicates the read is an instruction fetch INST is valid throughout the bus cycle INST is active only during external memory fetches during internal EPROM ROM fetches INST is held low Input for Memory Select (External Access) EA equal to a TTL-high causes memory accesses to locations 2000H through 3FFFH to be directed to on-chip EPROM ROM EA equal to a TTL-low causes accesses to these locations to be directed to off-chip memory EA e a 12 75V causes execution to begin in the Programming Mode EA has an internal pulldown so it defaults to execute from external memory unless otherwise driven EA is latched at reset Address Latch Enable or Address Valid Output as Selected by CCR Both pin options provide a latch to demultiplex the address from the address data bus When the pin is ADV it goes inactive (high) at the end of the bus cycle ADV can be used as a chip select for external memory ALE ADV is active only during external memory accesses
BUSWIDTH
NMI INST
EA
ALE ADV
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AUTOMOTIVE 8XC196KB
PIN DESCRIPTIONS (Continued)
Symbol RD WR WRL Name and Function Read Signal Output to External Memory RD is active only during external memory reads Write and Write Low Output to External Memory as Selected by the CCR WR will go low for every external write while WRL will go low only for external writes where an even byte is being written WR WRL is active during external memory writes Byte High Enable or Write High Output as Selected by the CCR BHE e 0 selects the bank of memory that is connected to the high byte of the data bus A0 e 0 selects that bank of memory that is connected to the low byte Thus accesses to a 16-bit wide memory can be to the low byte only (A0 e 0 BHE e 1) to the high byte only (A0 e 1 BHE e 0) or both bytes (A0 e 0 BHE e 0) If the WRH function is selected the pin will go low if the bus cycle is writing to an odd memory location BHE WRH is only valid during 16-bit external memory write cycles Ready Input to lengthen external memory cycles for interfacing with slow or dynamic memory or for bus sharing If the pin is high CPU operation continues in a normal manner If the pin is low prior to the falling edge of CLKOUT the memory controller goes into a wait state mode until the next positive transition in CLKOUT occurs with READY high When external memory is not used READY has no effect The number of wait states inserted into the bus cycle is controlled by the CCR Inputs to High Speed Input Unit Four HSI pins are available HSI 0 HSI 1 HSI 2 HSI 3 Two of which are shared with the HSO Unit (HSI 2 and HSI 3) The HSI pins are also used as the SID in Slave Programming Mode Outputs from High Speed Output Unit Six HSO pins are available (HSO 0 through HSO 5) HSO 4 and HSO 5 are shared with HSI 8-Bit High Impedance Input-Only Port These pins can be used as digital inputs and or as analog inputs to the on-chip A D converter These pins are also used as inputs to EPROM parts to select the Programming Mode 8-Bit Quasi-Bidirectional I O Port 8-Bit Multi-Functional Port All of its pins are shared with other functions 8-Bit Bidirectional I O Ports with Open Drain Outputs These pins are shared with the multiplexed address data bus which has strong internal pullups Bus Hold Input Requesting Control of the Bus Enabled by Setting WSR 7 Bus Hold Acknowledge Output Indicating Release of the Bus Enabled by setting WSR 7 Bus Request Output Activated when the bus controller has a pending external memory cycle Enabled by setting WSR 7
BHE WRH
READY
HSI
HSO PORT 0
PORT 1 PORT 2 PORT 3 and 4 HOLD HLDA BREQ
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AUTOMOTIVE 8XC196KB
ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings
Storage Temperature Voltage from VPP or EA to VSS or ANGND
b 60 C to a 150 C b 0 5V to a 13 0V
NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design
Voltage on Any Pin b 0 5V to a 7 0V to VSS or ANGND This includes VPP on ROM and CPU devices Power Dissipation 1 5W
WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability
OPERATING CONDITIONS
Symbol TA VCC VREF FOSC Parameter Ambient Temperature under Bias Digital Supply Voltage Analog Supply Voltage Oscillator Frequency Min
b 40
Max
a 125
Units C V V MHz
4 50 4 50 35
5 50 5 50 16
NOTE ANGND and VSS should be nominally at the same potential
DC CHARACTERISTICS
Symbol ICC IPD IREF IIDLE VIL VIH VIH1 VIH2 VOL Parameter
(Under Listed Operating Conditions) Min Typ 50 5 2 10
b 0 5V
Max 70
Units mA mA
Test Conditions XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V VCC e VPP e VREF e 5 5V XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V XTAL1 e 16 MHz VCC e VPP e VREF e 5 5V
VCC Supply Current ( b 40 C to a 125 C Ambient) Powerdown Mode Current A D Reference Supply Current Idle Mode Current Input Low Voltage Input High Voltage(1) Input High Voltage on XTAL1 Input on High Voltage on RESET Output Low Voltage
5 35
a0 8
mA mA V V V V V V V V V V V V V
0 2 VCC a 1 1 0 7 VCC 26
VCC a 0 5 VCC a 0 5 VCC a 0 5 03 0 45 15
IOL e 200 mA IOL e 3 2 mA IOL e 7 0 mA IOH e b 200 mA IOH e b 3 2 mA IOH e b 7 0 mA IOH e b 15 mA IOH e b 30 mA IOH e b 60 mA
VOH
Output High Voltage (Standard Outputs) Output High Voltage (Quasi-Bidirectional Outputs)
VCC b 0 3 VCC b 0 7 VCC b 1 5 VCC b 0 3 VCC b 0 7 VCC b 1 5
VOH1
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AUTOMOTIVE 8XC196KB
DC CHARACTERISTICS
Symbol ILI ILI1 ITL IIL IIL1 IIL2 HYST RRST CS
(Under Listed Operating Conditions) (Continued) Min Typ Max
g10
Parameter Input Leakage Current (Std Inputs) Input Leakage Current (Port 0) 1 to 0 Transition Current (QBD Pins) Logical 0 Input Current (QBD Pins) Logical 0 Input Current in Reset (ALE RD INST) Logical 0 Input Current in Reset (WR P2 0 BHE) Hysteresis on RESET Pin Reset Pullup Resistor Pin Capacitance (Any Pin to VSS)
Units mA mA mA mA mA mA mV
Test Conditions 0 k VIN k VCC b 0 3V 0 k VIN k VREF VIN e 2 0V VIN e 0 45V VIN e 0 45V VIN e 0 45V
g3
b 800 b 50 b9 b 700
250 6K 50 10
X pF FTEST e 1 0 MHz
NOTES (Notes apply to all specifications) 1 All pins except RESET and XTAL1 QBC (Quasi-bidirectional) pins include Port 1 P2 6 P2 7 2 Standard Outputs include AD0-15 RD WR ALE BHE INST HSO pins PWM P2 5 CLKOUT RESET Port 3 and 4 TXD P2 0 and RXD (in serial mode 0) The VOH specification is not valid for RESET Ports 3 and 4 are open drain outputs 3 Standard Inputs include HSI pins CDE EA READY BUSWIDTH NMI RXD P2 1 EXTINT P2 2 T2CLK P2 3 and T2RST P2 4 4 Maximum current per pin must be externally limited to the following values if VOL is held above 0 45V or VOH is held below VCC b 0 7V IOL on Output pins 10 mA IOL on QBD pins self limiting IOL on Standard Output pins 10 mA 5 Maximum current per bus pin (data and control) during normal operation is g3 2 mA 6 During normal (non-transient) conditions the following total current limits apply IOH is Self Limiting Port 1 P2 6 IOL 29 mA IOL 29 mA IOH 26 mA HSO P2 0 RXD RESET IOL 13 mA IOH 11 mA P2 5 P2 7 WR BHE IOH 52 mA AD0 - AD15 IOL 52 mA IOL 13 mA IOH 13 mA RD ALE INST CLKOUT 7 Typicals are based on limited number of samples and are not guaranteed The values listed are at room temperature and VREF e VCC e 5V
ICC MAX e 3 88 c Freq a 8 43 IIDLE MAX e 1 65 c Freq a 5 2 ICC TYP e 2 5 c Freq a 8 0 IIDLE TYP e 0 5 c Freq a 3 2
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Figure 5 ICC vs Frequency
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AUTOMOTIVE 8XC196KB
AC CHARACTERISTICS
Over Specified Operating Conditions Test Conditions Capacitance load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz The system must meet these specifications to work with the 8XC196KB Symbol TAVYV TLLYV TYLYH TCLYX TLLYX TAVGV TLLGV TCLGX TAVDV TRLDV TCLDV TRHDZ TRXDX FXTAL TOSC TXHCH TCLCL TCHCL TCLLH TLLCH TLHLH TLHLL TAVLL TLLAX TLLRL TRLCL TRLRH TRHLH TRLAZ TLLWL TCLWL TQVWH TCHWH TWLWH Parameter Address Valid to READY Setup ALE Low to READY Setup Non READY Time READY Hold after CLKOUT Low READY Hold after ALE Low Address Valid to Buswidth Setup ALE Low to Buswidth Setup Buswidth Hold after CLKOUT Low Address Valid to Input Data Valid RD Active to Input Data Valid CLKOUT Low to Input Data Valid End of RD to Input Data Float Data hold after RD Inactive Oscillator Frequency Oscillator Period (1 fXTAL) XTAL1 High to CLKOUT High or LOW(1) CLKOUT Period CLKOUT High Period CLKOUT Falling Edge to ALE Rising ALE ADV Falling Edge to CLKOUT Rising ALE ADV Cycle Time ALE ADV High Period Address Setup to ALE ADV Falling Edge Address Hold after ALE ADV Falling Edge ALE ADV Falling Edge to RD Falling Edge RD Low to CLKOUT Falling Edge RD Low Period RD Rising Edge to ALE ADV Rising Edge(3) RD Low to Address Float ALE ADV Falling Edge to WR Falling Edge CLKOUT Low to WR Falling Edge Data Stable to WR Rising Edge CLKOUT High to WR Rising Edge WR Low Period TOSC b 10 0 TOSC b 23
b5
Min
Max 2 TOSC b 75 TOSC b 60 No Upper Limit
Units ns ns ns ns(1) ns(1) ns ns ns
0 TOSC b 15
TOSC b 30 2 TOSC b 40 2 TOSC b 75 TOSC b 60
0 3 TOSC b 55 TOSC b 23 TOSC b 50 TOSC b 20 0 35 62 5 20 2 TOSC TOSC b 10
b 10 b 15
ns ns ns ns ns
16 286 110
MHz ns ns ns ns ns ns ns ns ns ns ns
TOSC a 10 10 15 4 TOSC
TOSC b 10 TOSC b 30 TOSC b 40 TOSC b 35 4 TOSC b 10 TOSC
TOSC a 10
25 TOSC a 25 TOSC a 25 5
ns ns ns ns ns
25
ns ns
15 TOSC a 5
ns ns
TOSC b 15
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AUTOMOTIVE 8XC196KB
AC CHARACTERISTICS
Over Specified Operating Conditions (Continued) Test Conditions Capacitance load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz The system must meet these specifications to work with the 8XC196KB Symbol TWHQX TWHLH TWHBX TWHAX TRHBX TRHAX Parameter Data Hold after WR Rising Edge WR Rising Edge to ALE ADV Rising Edge(3) BHE INST HOLD after WR RD Rising Edge AD8-15 Hold after WR RD Rising Edge BHE INST HOLD after RD Rising AD8-15 HOLD after RD Rising Min TOSC b 15 TOSC b 20 TOSC b 15 TOSC b 30 TOSC b 10 TOSC b 25 TOSC a 10 Max Units ns ns ns ns ns ns
NOTES 1 Typical specification not guaranteed 2 Assuming back-to-back bus cycles TOSC e 62 5 ns at 16 MHz TOSC e 100 ns at 10 MHz TOSC e 125 ns at 8 MHz
System Bus Timing
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AUTOMOTIVE 8XC196KB
Ready Buswidth Timing
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HOLD HLDA Timings
Symbol THVCH HOLD Setup 80C196KB 83C196KB CLKOUT Low to HLDA Low CLKOUT Low to BREQ Low HLDA Low to Address Float 80C196KB 83C196KB HLDA Low to BHE INST RD WR Float CLKOUT Low to HLDA High CLKOUT Low to BREQ High HLDA High to Address No Longer Float HLDA High to BHE INST RD WR Valid CLKOUT Low to ALE High
b 15 b 15 b5 b 20 b5
Description
Min 75 85
b 15 b 15
Max
Units ns
Notes 1
TCLHAL TCLBRL THALAZ
15 15 15 20
ns ns ns ns
THALBZ TCLHAH TCLBRH THAHAX THAHBV TCLLH
15 15
ns ns ns ns
15
ns
NOTE 1 To guarantee recognition at next clock
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AUTOMOTIVE 8XC196KB
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External Clock Drive
Symbol 1 TXLXL TXLXL TXHXX TXLXX TXLXH TXHXL Parameter Oscillator Frequency Oscillator Period (TOSC) High Time Low Time Rise Time Fall Time Min 35 62 5 TOSC b 51 TOSC b 51 TOSC b 73 TOSC b 73 Max 16 286 Units MHz ns ns ns ns ns
EXTERNAL CLOCK DRIVE WAVEFORMS
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AUTOMOTIVE 8XC196KB
AC TESTING INPUT OUTPUT WAVEFORMS
FLOAT WAVEFORMS
270679 - 7 AC Testing inputs are driven at 2 4V for logic ``1'' and 0 45V for a logic ``0'' Timing measurements are made at 2 0V for a logic ``1'' and 0 8V for logic ``0''
270679 - 8 For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loading VOH VOL level occurs IOL IOH s g15 mA
EXPLANATION OF AC SYMBOLS
Each symbol is two pairs of letters prefixed by ``t'' for time The characters in a pair indicate a signal and its condition respectively Symbols represent the time between the two signal condition points
Conditions H High L Low V Valid X No Longer Valid Z Floating
Signals A Address B BHE C CLKOUT D Data G Buswidth
L ALE ADV R RD W WR WRH WRI X XTAL1 Y Ready
AC CHARACTERISTICS
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT TIMING SHIFT REGISTER MODE Test Conditions TC e b 40 C to a 125 C VCC e 5 0V g10% VSS e 0 0V Load Capacitance e 80 pF Symbol TXLXL TXLXH TQVXH TXHQX TXHQV TDVXH Parameter Serial Port Clock Period(9) Serial Port Clock Falling Edge to Rising Edge(9) Output Data Setup to Clock Rising Edge Output Data Hold after Clock Rising Edge Next Output Data Valid after Clock Rising Edge Input Data Setup to Clock Rising Edge TOSC a 50 0 TOSC Min 6 TOSC 4 TOSC Max Unit ns
4 TOSC b 50 2 TOSC b 50 4 TOSC a 50 2 TOSC b 50 ns 2 TOSC b 50 2 TOSC b 50 2 TOSC a 50 ns ns ns ns ns ns
TXHDX(8) Input Data Hold after Clock Rising Edge TXHQZ(8) Last Clock Rising to Output Float
NOTES 8 Parameter not tested 9 Baud Rate Register t 8002H Baud Rate Register e 8001H
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AUTOMOTIVE 8XC196KB
The converter is ratiometric so the absolute accuracy is directly dependent on the accuracy and stability of VREF VREF must be close to VCC since it supplies both the resister ladder and the digital section of the converter
A to D CHARACTERISTICS
There are two modes of A D operation with and without clock prescaler The modes are shown in the table below In mode 2 with the clock prescaler disabled the maximum XTAL1 frequency is 8 0 MHz Accuracy will degrade at higher frequencies in this mode The frequency divider option is provided to obtain higher accuracy outside of the currently specified operating conditions
A D Converter Specifications
The specifications given below assume adherence to the operating conditions section of this data sheet Testing is performed in mode 2 with VREF e 5 12V and 8 MHz operating clock frequency
WAVEFORM
SERIAL PORT
SHIFT REGISTER MODE
SERIAL PORT WAVEFORM
SHIFT REGISTER MODE
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Clock Prescaler ON IOC2 4 e 0 Mode 1 158 States for Execution 26 33 ms 12 MHz
Clock Prescaler OFF IOC2 4 e 1 Mode 2 91 States for Execution 22 75 ms 8 MHz (Maximum)
NOTE IOC2 3 e 0 The No Sample and Hold feature is not available on the 8XC196KB device
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AUTOMOTIVE 8XC196KB
Parameter Resolution Absolute Error Full Scale Error Zero Offset Error Non-Linearity Differential Non-Linearity Channel-to-Channel Matching Repeatability Temperature Coefficients Offset Full Scale Differential Non-Linearity Off Isolation Feedthrough VCC Power Supply Rejection Input Resistance DC Input Leakage Sample Time (Prescaler on off) Input Capacitance
Typical (1)
Minimum 512 9 0
Maximum 1024 10
g6
Units Level Bits LSBs LSBs LSBs
0 25 g0 5
b 0 25 g0 5
15g25
0
lb 1
g4
LSBs LSBs LSBs LSBs(1) LSB C(1) LSB C(1) LSB C(1)
a2
g1
g0 1 g0 25
0
0 009 0 009 0 009
b 60 b 60 b 60
dB(1 2 4) dB(1 2) dB(1 2) X(1) mA States (3) pF
1K 0 15 8 3
5K 3
NOTES These values are expected for most parts at 25 C but are not tested or guaranteed An ``LSB'' as used here has a value of approximately 5 mV (See Automotive Handbook for A D glossary of terms 1 These values are not tested in production and are based on theoretical estimates and or laboratory test 2 DC to 100 KHz 3 One state e 125 ns 16 MHz 333 ns 6 MHz 4 Multiplexer Break-Before-Make Guaranteed
80C196KB FUNCTIONAL DEVIATIONS
The 80C196KB has the following problems 1 The HSI unit has two errata one dealing with resolution and the other with first entries into the FIFO The HSI resolution is 9 states instead of 8 states Events on the same line may be lost if they occur faster than once every 9 state times There is a mismatch between the 9 state time HSI resolution and the 8 state time timer This causes one time value to be unused every 9 timer counts Events may receive a time-tag one count later than expected because of this ``skipped'' time value
If the first two events into an empty FIFO (not including the Holding Register) occur in the same internal phase both are recorded with one timetag Otherwise if the second event occurs within 9 states after the first its time-tag is one count later than the first's If this is the ``skipped'' time value the second event's time-tag is 2 counts later than the first's If the FIFO and Holding Register are empty the first event will transfer into the Holding Register after 8 state times leaving the FIFO empty again If the second event occurs after this time it will act as a new first event into an empty FIFO 2 If an A D conversion in progress is aborted by starting a new A D conversion results of the second conversion may be inaccurate
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AUTOMOTIVE 8XC196KB
The work-around is to wait for the conversion in progress to finish before starting the second conversion Polling or an interrupt will detect the conversion completion 3 If the unsigned divide instruction (word or byte) is in the queue as HOLD or READY is asserted the result may be incorrect TechBit (MC1791) (B-step only ) 4 Make sure all inputs are tied high or low and not left floating 5 Indexed and indirect operations relative to the stack pointer (SP) work differently on the 80C196KB than on the 8096BH On the 8096BH the address is calculated based on the un-updated version of the stack pointer The 80C196KB uses the updated version The offset for POP SP and POP nn SP instructions may need to be changed by a count of 2 6 The VPD pin on the 8096BH has changed to a VSS pin on the 80C196KB
DIFFERENCES BETWEEN THE 80C196KA AND THE 80C196KB
The 8XC196KB is identical to 8XC196KA except for the following differences 1 ALE is high after reset on the 80C196KB instead of low as on the 80C196KA 2 The DJNZW instruction is not guaranteed to work on the 80C196KB (A-step only ) 3 The HOLD HLDA bus protocol is available on the 80C196KB
OTHER DESIGN CONSIDERATIONS (KB B-0 to KB C-1)
1 The NMI pin on the KB ROM (C-1) has a weak pulldown IIH1 max is 100 mA The KB ROM (B-0) did not have a pulldown on NMI If KB ROM (B-0) designs have NMI tied to VCC the NMI pin must be tied to VSS If NMI is tied to VSS or is floating it is okay 2 The ALE RD and INST pins on the KB ROM (C-1) have stronger pullups during RESET than on the KB ROM (B-0) IIL1 is b 7 mA on the KB ROM (C-1) compared to b 1 2 mA on the KB ROM (B-0) Designs which pull these pins low to enter ONCE mode must have strong enough pulldowns to overcome the pullups 3 Pin on the PLCC package on the KB ROM (B-0) was the CDE pin That function did not work so the pin was assigned to VSS On the KB ROM (C-1) this pin is tied directly to VSS on the device and MUST be tied to VSS externally 4 Several AC DC specifications have changed (See Data Sheet Revision History review them carefully )
CONVERTING FROM OTHER 8096BH FAMILY PRODUCTS TO THE 80C196KB
The following list of suggestions for designing an 809XBH system will yield a design that is easily converted to the 80C196KB 1 Do not base critical timing loops on instruction or peripheral execution times 2 Use equate statements to set all timing parameters including the baud rate 3 Do not base hardware timings on CLKOUT or XTAL1 The timings of the 80C196KB are different than those of the 8X9XBH but they will function with standard ROM EPROM Peripheral type memory systems
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AUTOMOTIVE 8XC196KB
21 TCLLH min max has changed from b 5 ns 15 ns to b 10 ns 10 ns 22 TLHLL min max has changed from TOSC g12 ns to TOSC g10 ns 23 TAVLL has changed from TOSC b 20 ns to TOSC b 30 ns 24 TLLRL has changed from TOSC b 40 ns to TOSC b 35 ns 25 TRLCL min max has changed from 5 ns 30 ns to 4 ns 25 ns 26 TRLRH has changed from TOSC b 5 ns to TOSC b 10 ns 27 TRLAZ has changed from 12 ns to 5 ns 28 TCHWH min max has changed from b 10 ns 10 ns to b 5 ns 15 ns 29 TWLWH min max has changed from TOSC b 30 ns to TOSC b 15 ns 30 TWHQX has changed from TOSC b 10 ns to TOSC b 15 ns 31 TWHLH min max has changed from TOSC b 10 ns TOSC a 15 ns to TOSC b 20 ns TOSC a 10 ns 32 TWHBX has changed from TOSC b 10 ns to TOSC b 15 ns 33 TWHAX has changed from TOSC b 50 ns to TOSC b 30 ns 34 TRHAX has changed from TOSC b 50 ns to TOSC b 25 ns 35 Functional deviation number 1 has been removed (DJWZ is now functional) 36 Functional deviation number 3 has been removed (SIO framing flag now works correctly) 37 Functional deviation number 5 has been removed (SIO RI now correctly generated) 38 Functional deviation number 6 has been corrected The divide during HOLD bug has been fixed 39 The section ``Other Design Considerations KB B-0 to KB C-1'' has been added
DATA SHEET REVISION HISTORY
This is the -005 revision of the 8XC196KB data sheet and is valid for devices marked with a ``F'' or ``G'' at the end of the topside tracking number The following differences exist between the -004 revision and the -005 revision 1 All performance related data is now quoted at 16 MHz The maximum clock rate has changed from 12 MHz to 16 MHz 2 Max power dissipation changes from 0 43W to 1 5W 3 ICC max has changed from 60 mA to 70 mA 4 ICC typical has changed from 40 mA to 50 mA 5 IREF typical has changed from 1 mA to 2 mA 6 IIDLE has changed from 25 mA to 35 mA 7 VIH2 min has changed from 2 4V to 2 5V 8 VOH1 test condition for VCC b 0 3V has changed from b 7 mA to b 15 mA 9 ITL has changed from b 650 mA to b 800 mA 10 IIL1 has changed from b 1 2 mA to b 9 mA 11 IIL1 now only applies to ALE RD and INST 12 RRST max has changed from 100 KX to 50 KX 13 Added spec for RESET pin hysteresis and IIL2 for WR P2 0 and BHE 14 TAVYV has changed from 2 TOSC b 85 ns to 2 TOSC b 75 ns 15 TLLYV has changed from TOSC b 72 ns to TOSC b 60 ns 16 TAVGV has changed from 2 TOSC b 85 ns to 2 TOSC b 75 ns 17 TAVDV has changed from 3 TOSC b 65 ns to 3 TOSC b 55 ns 18 FXTAL max has changed from 12 MHz to 16 MHz 19 TOSC min has changed from 83 ns to 62 5 ns 20 TXHCH min has changed from 40 ns to 20 ns
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